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Design Guidelines for TERIDIAN 78P235x LIUs
Figure 9. Single and Dual Core Transformer Diagrams (top view)
SUPPLEMENTAL SURGE PROTECTION
?
This section describes the recommended protection circuitry needed in order to meet the surge immunity
requirements defined in the ITU K.41 and GR-1089 for indoor signal lines. Before implementing such protection
circuitry, two items should be noted:
1. Teridian Semiconductor LIUs are protected against ESD (Electric Static Discharge) and rated at 2000V
unless otherwise noted.
2. The LIU should be isolated from the line via a transformer, which will prevent common mode spikes from
damaging the transceiver.
For designs where the aforementioned protection is not enough, Teridian has verified the following circuits to
satisfy the ITU and Telcordia requirements listed above. Method 1 is a low cost protection circuit with minimal
effects on STM1e/E4 transmit pulse shapes or return loss performance.
For methods 2 (with SRV0504) and 3 (with LCO3-3.3), system vendors should make provisions to tune the return
loss characteristics according to their design.
Method 1
BAV99
1
6
BNC
C88
5
1
DNP
3
4
BAV99
Method 2
Method 3
1
6
BNC
1
1
6
1
6
5
BNC
1
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
3
5
4
2
3
5
4
3
4
LCO3-3.3
SRV0504
Figure 12: Typical Connection Diagram for Both Tx and Rx Interface
NOTE: Surge protection diodes protect the core of the line and are not used for ESD immunity at the faceplate.
Use proper grounding techniques and system enclosures for compliance to EMI, EMC, and ESD Immunity
requirements.
Page 7 of 15
? 2008 Teridian Semiconductor Corp.
Rev 2.1
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相关PDF资料
79-WHITE-1"X60YD TAPE GLASS CLOTH 1"X 60YD WHT
79059-2701 CONN RECEPT R/A 50POS 4-40 SCSI
79059-2702 CONN RECEPT R/A 68POS 4-40 SCSI
79059-2726 CONN RECEPT R/A 50POS 2-56 SCSI
79278 TAPE CLR ESD YEL STRIPE 2"X72YDS
796014-2 CONN CHAMP GUIDE PIN .050
796055-2 CONN RCPT 68POS .8MM R/A
796068-1 CONN RCPT 40POS .050 VERT
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